Freedom CAD is Cadence’s Service Bureau of the Month
Freedom CAD has been recognized by Cadence as their Service Bureau of the Month. Cadence sited Freedom CAD’s expertise with their Allegro PCB Design Software and participation in Allegro BETA program were key contributors to this selection.
Visit Cadence Design Systems for the details!
Freedom CAD’s McCurdy Sets March Orange County IPC Meeting Agenda
Freedom CAD’s Scott McCurdy, President of the Orange County chapter of the IPC Designers Council, has announced the agenda for the March Meeting. The meeting is set for Wednesday, March 17th, from 11:30 am – 1:30 pm at Broadcom Corp’s. Irvine facility.
Charles Pfeil, Engineering Director at Mentor will be presenting “Effective Design Methods for Very Large BGAs”.
Mr. Pfeil has been in the PCB design industry for 40+ years and literally “wrote the book” on this subject. There are many benefits to using the BGA package; however its greatest asset – the ability to provide an extremely dense array of thousands of pins – also turns out to be a tremendous problem for PCB designers. The BGA density and pin count continues to increase; yet, our ability to effectively design with these devices has not kept pace.
Fortunately, significant advancements in PCB fabrication technology have enabled further miniaturization in the manufacturing process. These improvements, along with new software and design methods specifically for BGAs provide a means to successfully design using these devices. Mr. Pheil will explore the impact of dense BGAs with high pin-count on PCB design and provides solutions for inherent design challenges.
In addition, Vern Wnek, of Broadcom’s Chip Planning and Packaging Group will be presenting “Let your PCB Layout Team help you be SUCCESSFUL”
Mr. Wnek is a CID and a PCB Manager and the Central Library Manager for Broadcom Corporation in Irvine, CA. He has 30 years experience in the industry with PCB Layout Designs and EDA tools for DFM, DFA, and DFT requirements and is a multiple Co-Patent holder for Routing Optimization for Ball Grid Array Packaging for PCB Design. He will discuss how to create a successful team process and approach for Chip IO Planning and PCB Layout Optimization to help save your customer time and money.
Freedom CAD Participates in Virtual PCB Conference
Freedom CAD Service’s, senior printed circuit board designer, Robert Jardon, is presenting at Virtual PCB Conference on March 2-4. The Virtual PCB is the industry’s first virtual conference and trade show for the PCB design, fabrication and assembly markets.
The conference includes presentations on:
- Tin Whiskers: Are they behind the Toyota recalls?
- Printed Electronics vs.Traditional Electronics
- DDR3 Design and Analysis
- Easy (and Cost-Effective Ways) to Prototype Faster
- How to Plan your Design to Save Layers and Time
- LEDs and PCBs
- Library Management
- Emerging Technologies in Electronics
- Rigid/Flex
- Solderability and Reliability
- Flip Chip
Freedom CAD’s Robert Jardon is presenting “How to Plan Your Design to Save Layers and Time”.
Robert Jardon has earned a worldwide reputation for developing high density, high complexity interconnect design solutions where other designers have been less successful. He shared his 30 years of interconnection technology experience, 20 of those years using Cadence Allegro, in a presentation describing how an effective planning methodology that includes Cadence’s Interconnect Flow Planner (IFP) can reduce layer counts and save time and money during the printed circuit board layout process.
The trade show can be found on-line at: http://www.virtual-pcb.com
Freedom CAD Participates in Cadence Virtual Conference
Freedom CAD Service’s, senior printed circuit board designer, Robert Jardon, presented at Cadence’s Virtual Conference on December 2nd, 2009. The Virtual Conference introduced Cadence’s Allegro and OrCAD Version 16.3 Printed Circuit Board Design Software. Robert’s session addressed Optimizing Complex Designs by utilizing Cadence Allegro’s GRE Interconnect Flow Planner (IFP).
Robert Jardon has earned a worldwide reputation for developing high density, high complexity interconnect design solutions where other designers have been less successful. He shared his 30 years of interconnection technology experience, 20 of those years using Cadence Allegro, in a presentation describing how an effective planning methodology can reduce layer counts and save time and money during the printed circuit board layout process.
Following the presentation, Robert fielded questions from a number of participants about the IFP tool and planning process..
Click play below to view the presentation.
For a link to the Cadence Press Release regarding the Cadence Virtual Conference please go to: http://www.cadence.com/cadence/newsroom/press_releases/pages/pr.aspx?xml=102709_advance
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.