Freedom CAD Service’s, senior printed circuit board designer, Robert Jardon, presented at Cadence’s Virtual Conference on December 2nd, 2009. The Virtual Conference introduced Cadence’s Allegro and OrCAD Version 16.3 Printed Circuit Board Design Software. Robert’s session addressed Optimizing Complex Designs by utilizing Cadence Allegro’s GRE Interconnect Flow Planner (IFP).
Robert Jardon has earned a worldwide reputation for developing high density, high complexity interconnect design solutions where other designers have been less successful. He shared his 30 years of interconnection technology experience, 20 of those years using Cadence Allegro, in a presentation describing how an effective planning methodology can reduce layer counts and save time and money during the printed circuit board layout process.
Following the presentation, Robert fielded questions from a number of participants about the IFP tool and planning process..
Click play below to view the presentation.
For a link to the Cadence Press Release regarding the Cadence Virtual Conference please go to: http://www.cadence.com/cadence/newsroom/press_releases/pages/pr.aspx?xml=102709_advance
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.