Overview of a Complete Board Redesign
The Digital Driver Detector (DDD) board was part of a low cost test platform for mixed signal, analog, linear and discrete devices. It was redesigned to eliminate component obsolescence, use all SMT devices for manufacturing ease and solve low frequency (< 1MHz) gaps or dead zones for driving and receiving data. This was accomplished without disturbing the operating system software. Because of the redesign, additional features were realized with a rewrite of the operating system software. One of the benefits of the redesign was increasing the number of channels from 8 to 16, basically putting the function of two DDD boards onto one board’s form factor.
Roll your mouse over the image to compare before and after images.
At the heart of the new design was the Lattice Semiconductor XPLD programmable device that incorporates almost all of the digital logic. This includes all of the active CPU interface logic, the Altera FPGA, the four GALs and the eight channels worth of pattern Flip-Flops that drive the Analog driver/receiver circuitry. Since the original Analog Devices programmable delay device (AD9501) was obsolete, a ROM look-up-table (LUT) was used to translate the old programmable delay data into data understood by the new devices. The XPLD also implemented a standard I2C interface to communicate with the new AMI FS7145 programmable clock generator device that replaced an obsolescent part (ICD2051). The clock operating range of the old hardware and software was 320 KHz to 14 MHz.
As mentioned the clock and delay devices were changed. They generated the leading edge (LE) and trailing edge (TE) programmable delays for each channels driven data. To match the function of the AD9501, each of the eight channels used a course delay device (Dallas DS1023-200) and a fine delay device (Micrel SY100EP195V). Since the Micrel device has LVPECL signal levels in and out, a translator device (Micrel SY100EP23L) converts the signals out of the 195 to LVTTL to be accepted by the course delay Dallas device. The course delay device was capable of 2 ns/step with a total of 255 steps, while the fine delay device was capable of 10 ps/step for a total of 12.5 ns including propagation delay. This yielded a typical total delay of 522.5 ns per one of four Verniers and allowed coverage of the entire phase period for clock frequencies as slow as 478.5 KHz. However, 320 KHz was the original goal and thus an extra change was needed to add four Verniers for a total of eight and yielded a new low end of 245 KHz. The new upper frequency limit was extended from 14 MHz to 20 MHz with a minor software update.
The analog driver/receiver circuitry was kept but converted to use all SMT devices to minimize its board footprint. All of this circuitry was now placed on the main board, thus eliminating the two daughter cards and its associated connectors. Since the new circuitry is basically the same as the old, the performance and accuracy followed.Back to Electrical Engineering Overview