This project was a RoHS compliant design that fit within a four physical lane PCI Express (PCIe) form factor as defined in the PCIe 2.0 specification. The height of the card was allowed to extend past the specification limits to accommodate the placement and routing of the four DDR2 memory DIMM sockets. This design was not required to support Hot Swap, WAKE, and SMB functions. The Xilinx reference designs, ML555 and ML561, were used as starting points for the electrical design of this board. The PCIe circuitry was implemented according to the ML555 reference design and the DDR2 and QDR II SRAM memory interfaces were implemented from the ML561 reference design.
The Xilinx Virtex 5 FPGA device, part number XC5VLX85T-1FF1136C, was at the core of this design. Firmware and signal pin assignments for the FPGA were provided by the customer. A pair of external 200 MHz clock sources was required by the FPGA to internally generate the DDR and QDR memory clocks. At power on, the FPGA firmware was downloaded from the configuration SPI flash device. Following configuration the device allowed and controlled PCIe accesses to the on board DDR2 and QDR SRAM memory devices.
Memory consisted of four 22.5° DIMM sockets that support 2GB, 4GB, and 8GB DDR2 memory modules for a maximum total of 32GB of DDR2 memory. The memory modules support ECC and parity, and speeds from 266 MHz to 566 MHz. A single Samsung 8 MB QDR II SRAM device was also on board supporting 300 MHz clock speeds.
A manual reset switch was implemented to reset the FPGA as required during test. Further LED status indicators were provided for the following functions:
Power supply voltages and currents were implemented for the following:
The required voltages were created from the 3.3V and 12V power supplied over the PCIe bus. All voltages were monitored by a Lattice in-system programmable power supply monitoring, sequencing and margining controller. Freedom CAD engineers supplied the firmware for this device which also provided power on reset to the card.Back to Electrical Engineering Overview